In the design and manufacture of ASIC (Application specific integrated circuit) chips and microprocessor chips it is conventional practice to provide the chip designer with a library of conventional circuits from which to chose and generate his/her design. The chip designer chooses from this library the necessary circuits and connects them to form the desired chip configuration. In the case of microprocessors the designs and parameters of the library circuits are fixed thus imposing certain constraints on the chip designer. In the case of ASIC chips not only are the designs fixed but also the rules of wiring are fixed thus imposing additional constraints. Thus the designer is constrained by the circuit design and in the case of ASIC chips the rules in using the various circuits.
One of the library circuits which can be used by a chip designer is a phase locked loop circuit. Phase locked loops (PLLs) are widely used in many different applications. They are used to perform two or three different functions. A principal function is to lock or align the output clock of a circuit with the clock input. Another function is to multiply (i.e. increase) or divide (i.e. decrease) the output frequency of a circuit with respect to the input frequency. Another function of a phase locked loop is to provide clock recovery, i.e. to attenuate the input jitter associated with input signals and recover clock from jittery input data.
In providing a phase locked loop circuit, as with other circuits, it is desirable to provide a circuit that is versatile, i.e. one that can be used in a wide variety of applications and environments. Specifically, one challenge is to provide a phase locked loop, which is an analog circuit, which can be used in digital CMOS technology in which a good deal of substrate noise is generated. It is also desirable to provide a PLL that is operational over a broad frequency range. Moreover it is necessary in the design of ASIC chips to compensate for delays induced in clock distribution trees as well as any delays that might be induced by dividers in the feedback portion of the circuit when frequency is being multiplied, which often occurs when the signal is being received from a relatively low frequency source, such as a card, and is being multiplied for use on a chip.
It is also desirable to reduce jitter in both the high frequency range as well as in the lower frequency ranges. To further complicate matters, a recent design problem that has emerged is that associated with reduced power supply voltages at which the chips operate, these being as low as 5, or 3, or even as low as 2 volts. At these low power supply voltages conventional charge pumps in many cases are not adequate to maintain the loop in locked condition. Moreover, overriding all of these constraints and conditions is the need to use as little "real estate" i.e. surface area of the chip as possible for the circuit, which has been and continues to be a major consideration in the design of PLLs as well as other circuits.
Hence it is a object of the present invention to provide a PLL suitable for use in microprocessor chips as well as ASIC chips that is versatile, has essentially zero feed-back delay,is quite insensitive to substrate and power supply noise, is conservative of real estate, and can operate over a wide range of frequencies.